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- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.
- Refactor MemoryInitSpec for improved results readability
Context:
PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
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emission-options flags swapped to match their functionality
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Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.
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This fixes an off by one error, where 3 was erroneously
accepted as in-bounds for a memory of depth=3
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* Add FileInfo to asyncResetAlwaysBlocks
Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).
RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.
Async always blocks don't provide their only FileInfo, so there are no line numbers.
This commit gives async always block the extra FileInfo to show line numbers for them.
This code:
```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission
class Test extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val valid = RegInit(false.B)
valid := io.in
io.out := valid
}
object Test extends App {
new ChiselStage().execute(Array(), Seq(
ChiselGeneratorAnnotation(() => new Test()),
CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
))
}
```
will generate this Verilog:
```verilog
module Test(
input clock,
input reset,
input io_in,
output io_out
);
reg valid; // @[Playground.scala 10:22]
assign io_out = valid; // @[Playground.scala 12:10]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[Playground.scala 10:22]
valid <= 1'h0; // @[Playground.scala 10:22]
end else begin
valid <= io_in; // @[Playground.scala 11:9]
end
end
endmodule
```
they have correct line numbers (10, 10, 11).
* Add test for async always block line numbers
* Add comment for review
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* Fix unreachable code warning by changing match order
Simulation Statements did not previously extend IsDeclaration, but now
they do so their match blocks need to be above IsDeclaration.
* Handle MemoryNoInit case in RtlilEmitter
* Remove use of deprecated logToFile
* Fix uses of LegalizeClocksTransform
Replaced all uses of LegalizeClocksTransform with
LegalizeClocksAndAsyncResetsTransform.
* Remove use of CircuitForm in ZeroWidth
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Fix bugs related to arithmetic ops inlined into a mux leg. Add formal
equivalence checks to lock in this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This should fix issue #2436
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* Add renamemap.MutableRenameMap which includes these methods without
deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
undeprecated a while ago
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Change AnnotationSeq underlying from List to Seq
It was nothing but pointless copying.
* Make propagateAnnotations faster
There was lots of expensive logic for very little benefit.
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1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix.
2. Add CustomRadixConfigFileAnnotation to output a JSON config file so
users can generate scripts on their own.
Reviewed-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: sinofp <sinofp@tuta.io>
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The ANTLR-generated concrete syntax tree (CST) takes up much more memory
than the parsed .fir file. By using a Listener, we can construct the
FIRRTL AST live with CST construction and null out the CST as we consume
pieces of it. Not only does this improve performance, it drastically
reduces max memory use for the parser.
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Tweak the grammar to handle references without left-recursion. Also
split references and subreferences out from the regular expression rule
to make their parsing more efficient.
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(#2423)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Also remove all related APIs:
ComposableOptions
HasParser
CommonOptions
HasCommonOptions
FirrtlExecutionOptions
HasFirrtlOptions
FirrtlExecutionResult
FirrtlExecutionSuccess
FirrtlExecutionFailure
ExecutionOptionsManager
firrtl.stage.DriverCompatibility.firrtlResultView
logger.Logger.makeScope
OutputConfig
SingleFile
OneFilePerModule
* Change default LogLevel to None which means "unset"
Logger.getGlobalLevel then returns LogLevel.Warn when the current value
is LogLevel.None. This preserves the behavior of the default being
"Warn" but now uses LogLevel.None to indicate "I'm not setting the
value." This resolves issues where it was not possible to tell if
annotations were actually setting the log level or if the default level
of warn was just being filled in.
Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: sinofp <sinofp@tuta.io>
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Co-authored-by: sinofp <sinofp@tuta.io>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* remove firrtl.Utils.get_flip.
* remove firrtl.Utils.indent.
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* Add option to disable random mem/reg init
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
* fix for code review.
Co-authored-by: SharzyL <me@sharzy.in>
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An application like barstools may contain a main that loads an annotations file containing
annotation classes that are not on it's classpath. This change allows unknown annotations
to be preserved by wrapping them in a UnrecognizedAnnotation. If annotations are then output
to a file, they will be unwrapped during serialization
This feature can be enabled via an AllowUnrecognizedAnnotations annotation
Co-authored-by: chick <chick.markley@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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We never tested the case where the width of the
numerator was less than the denominator.
This should fix any issue with this combination.
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+ correct the Error Info of "At least one dedupable annotation..."
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Reset, AsyncReset, Interval, attach, assert, assume, and cover have all
been added as keywords but not added to the allowlist for parsing as
ids.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point. Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.
Fixes #2379.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Demonstrate a couple failing cases
* Have TopWiring ignore unnamed declarations as potential sources
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* Have Flatten & InlineInstances remove their annotations
* Format
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* Added RTLIL Backend.
* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.
* Fix build on scala 2.13
* Add additional equivalence test, make some bugfixes and perf opts to the emitter.
* Final changes as requested by Kevin, code cleanup, add support for formal cells.
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The test was leaving the test directory in a dirty state that would fail
on a rerun. Fix the test so that it can be run multiple times in a row.
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This required also bumping sbt-scalafix to bring in a newer version of
semanticdb. The new version of semanticdb had an issue with a regex in
SMTLib, fixed by fixing the way '$' is escaped in the regex.
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BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
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* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs
Co-authored-by: Jack Koenig <koenig@sifive.com>
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We treat it as an assertion that the stop will
never be enabled. stop(0) will still be ignored
(but now demoted to a info from a warning).
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* Fix dshl zero-width shift behavior
Add a special case for dshl handling in the ZeroWidths pass. If one
expression is shifted by a second, zero-width expression, just return
the first expression. This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix dshl zero-width shift behavior
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Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.
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