sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-08-25	Removed IntWidth, now only use LongWidth. Now do width inference for ↵	azidar
	Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
2015-08-25	Added width check pass with tests. #22.	azidar

2015-08-24	Temporarily deprecated the flo backend until I fix it	azidar

2015-08-24	Added BigInt error if passed a string without starting with a b or h	azidar

2015-08-20	Added tests, cleaned up repo	azidar

2015-08-20	Added Poison node. Includes tests. #26.	azidar

2015-08-20	Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.	azidar

2015-08-20	Fixed bigint library to correctly extract bits from UIntValue. #19.	azidar

2015-08-19	Added beginning of constant propagation pass, doesn't work	azidar

2015-08-19	Switched to new bigint library	azidar

2015-08-19	Check Neg UInt in the parser	azidar

2015-08-19	Fixed width inference bug where constraints were propagating backwards.	azidar
	Updated tests to match. #29.
2015-08-18	Fixed width inference for static shift left, #18	azidar

2015-08-18	Fixed verilog emission from rand to random	azidar

2015-08-18	Fixed bug in MinusWidth where it was adding instead of subtracting widths	azidar

2015-08-18	Fixed so its length is greater than what it connects to. Changed shr to be ↵	azidar
	extract, not >>
2015-08-18	Emit random initialization instead of zero initialization for Verilog reg	azidar

2015-08-17	Removed leading zeros from UInt constants	azidar

2015-08-17	Fixed bug where equality between expressions was incorrect, leading to	azidar
	an optimization that eliminated some when statements. Added test case.
2015-08-17	Added tests for shl and mem. Fixed bug in verilog output of mem size.	azidar

2015-08-05	Added type inference before gender check	azidar

2015-08-05	Fixed bug in temp elimination.	azidar

2015-08-04	Added check for reading from outputs with flips	azidar

2015-08-04	Added () around width printers	azidar

2015-08-04	Added verilog keywords to uniquify them	azidar

2015-08-04	Fixed reading from instance's input ports. Fixed unique naming bug.	azidar

2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
	invalid <> assignments.
2015-08-03	Added concrete syntax for EmptyStmt()	azidar

2015-08-03	Fixed performance bug in Split Expressions. Changed delin for connect ↵	azidar
	indexed. Fixed various broken tests.
2015-07-31	Fixed (?) resolve genders pass	azidar

2015-07-31	Reading from output ports no longer causes errors	azidar

2015-07-31	Fixed inferred type of bits and bit	azidar

2015-07-31	Fixed compiletime error, whooops	azidar

2015-07-31	Allow bit operations on sints	azidar

2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar

2015-07-30	Added module name to error messages.	azidar

2015-07-30	Updated error and feature tests. Fixed bug in detecting incorrect genders	azidar

2015-07-30	Added eqv for bitwise equality, and change eq to be arithmetic equality	azidar

2015-07-30	Added primitive linking to firrtl-test-main	azidar

2015-07-30	Started adding linking support	azidar

2015-07-30	Updated lots of tests so they pass. Found one bug in expand whens	azidar

2015-07-29	Added linux zip	Adam Izraelevitz

2015-07-29	Finished supporting Chisel 2.0 Ref Chip	Adam Izraelevitz

2015-07-29	Add bigint support.	Adam Izraelevitz

2015-07-28	Integrated bigint. Mostly works, but getting "cast" error for make Test.	Adam Izraelevitz

2015-07-22	Fixed verilog so it emits non-random inital values. Changed Not to be	Adam Izraelevitz
	correct.
2015-07-21	Firrtl generates verilog that compiles, but does not work	Adam Izraelevitz

2015-07-21	Fixed bug in fix :P	azidar

2015-07-21	Fixed removing non-referenced components	azidar

2015-07-21	Made things go faster. Still in progress. Expand when now removes	Adam Izraelevitz
	non-referenced declarations that are not instances, but it doesn't work right now.