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Changed DefMemory to be a non-vector type with a size member
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AST -> String). Uses ANTLRv4 to generate concrete syntax parser
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Change of FIRRTL semantics!
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ASIC backend.
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Assignments to a register are no longer affected by enclosing when
statements:
when p :
reg r : UInt,clk,reset
r := a
will lower to:
reg r : UInt,clk,reset
r := a
instead of:
reg r : UInt,clk,reset
when p : r := a
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catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
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is unneeded
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Code like
add(UInt<1>(1), SInt<1>(1))
was resulting in Verilog like
$signed(1'h1) + $signed(1'sh1)
which is incorrect: it computes -2, not 0. The fix is to zero-extend the
unsigned operand, e.g.
$signed({1'b0,1'h1}) + $signed(1'sh1)
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conditional assignment
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Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
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Updated tests to match. #29.
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extract, not >>
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an optimization that eliminated some when statements.
Added test case.
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invalid <> assignments.
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indexed. Fixed various broken tests.
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