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Code like
add(UInt<1>(1), SInt<1>(1))
was resulting in Verilog like
$signed(1'h1) + $signed(1'sh1)
which is incorrect: it computes -2, not 0. The fix is to zero-extend the
unsigned operand, e.g.
$signed({1'b0,1'h1}) + $signed(1'sh1)
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conditional assignment
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Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
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Updated tests to match. #29.
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extract, not >>
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an optimization that eliminated some when statements.
Added test case.
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invalid <> assignments.
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indexed. Fixed various broken tests.
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