| Age | Commit message (Collapse) | Author |
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Fixes #147
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Transforms are new unit of modularity within the compiler.
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Add unit tests for splitting expressions and padding widths
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RemoveValidIf, SplitExpressions, and PadWidths
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This is to start moving stuff out of Emitter and into separate passes
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Changed initialization to assign the correct number of random bits.
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Fixes #133
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Fixes #113 and Fixes #150
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Make EmptyExpression part of WIR
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Change Field from IsDeclaration to HasName
Make WDefInstance an IsDeclaration
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time uses LazyLogging, also delete import PrimOps._ (cyclic reference)
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the leaf directions are the same
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easier testing, because we don't the source locator information to say a test fails
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Also add pass to Verilog Compiler list of passes
This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
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Make loweredName a public utility function of the Pass
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Almost all of the code was already there. This is cleaner (and faster)
than calling tpe(Expression).
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