aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-02-01Suport ir.SubAccess in Utils.splitRef (#2021)Schuyler Eldridge
* Add SubAccess case to Utils.splitRef Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Update Utils.splitRef to use IR types Change Utils.splitRef to use the actual IR types instead of their WIR aliases. Update the Scaladoc note to reflect this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-01ConstantPropagation: make RemoveValidIf an optional dependency (#2027)Kevin Laeufer
This allows ConstantPropagation to be used in cases where ValidIfs need to be maintained, e.g., in the formal backend. Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
Fixes bug with mul or div followed by cat. Also fixes some Verilog lint issues.
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
* Check Unidoc on all versions of Scala It is required for publishing and we publish every version * Fix conflicting cross-version suffixes issue When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version for the fuzzer and benchmark projects even though they aren't really relevant to the command. This may be a misconfiguration or a bug in the unidoc plugin. Whatever the case, simply making it possible for them to use the same version of Scala as the firrtl project (on which they depend) fixes the issue. * Match versions of Scala in build.sbt and CI * Fix unidoc issues in 2.13.4 There is some bug in ScalaDoc not finding some links in firrtl.options so those links were made absolute as a workaround.
2021-01-20Cleanup some warnings (#2032)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-20Add --dont-fold option to disable folding prim ops (#2040)Schuyler Eldridge
This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
Fix scalafmtCheckAll failures that snuck through
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
This is done by having LowerTypes uses two RenameMaps instead of one for each module. There is one for renaming instance paths, and one for renaming everything within modules. Also add some utilities: * TargetUtils for dealing with InstanceTargets * RenameMap.fromInstanceRenames
2020-12-11fix scaladoc for ReferenceTarget (#2014)Megan Wachs
2020-12-10Add newline in the end of LoFIRRTL file (#2015)XinJun Ma
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-02Fix subaccess (#1984)Jiuyang Liu
* add test for RemoveAccessesSpec. * fix nested SubAccess bug. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-30Add SortModules Transform (#1905)Schuyler Eldridge
* Add SortModules to transform to def-before-use Adds a new transform, SortModules, that transforms a FIRRTL circuit to enforce an invariant of modules and external modules being defined before use. This transform is left as optional in the event that a user may wish to have a quick way of getting the circuit to respect this property as may be expected of some other tool, e.g., MLIR. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of SortModules transform Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-23add weak and strong to Utils.v_keywords (#1983)Tim Snyder
Verilator 4.034 was complaining about wires being named weak and strong because those are SV 2009 keywords. Added them to the Utils.v_keywords list
2020-11-17Make MultiTargetAnnotation.targets a def (#1969)Jack Koenig
* Make MultiTargetAnnotation.targets a def This enables the annotation writer to choose their own underlying data structure * Update MultiTargetAnnotation ScalaDoc Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-16make LazyLogging log to console by default. (#1961)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
* smt: add test for write port collision * smt: add missing call to insertDummyAssignsForMemoryOutputs * smt: fix typo in write port code Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-10Refactor emiter (#1879)Jiuyang Liu
* split big Emitter to submodules. * fix all deprecated warning. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
* smt: add tests for assert name clashes * smt: ensure unique signal names with a namespace this fixes issues #1934
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
* Make Stage.run protected Change the access modifier of Stage.run from no modifier to protected. This method is really an internal API that the user implements with the main entry point for a Stage being "execute" or "transform". By allowing users to access "run" they can bypass checks, mandatory file reads/writes, and wrappers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Make FirrtlStage.run protected Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
Overflow of 32-bit Int would cause any negative literal value equal to -(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
* Also clean up VerilogMemDelaySpec structure
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-30Speed up writing CustomFileEmission with buffering (#1906)Jack Koenig
Also speed up common case of Array[Byte]
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
Both use EliminateTargetPaths to duplicate modules based on annotations. Currently, EliminateTargetPaths API is a little too limited so it duplicates more than it should which effectively breaks Dedup whenever DontTouchAnnotations are present. Also, make ConstProp and DCE treat all HasDontTouches as local annotations even if they are instance annotations. This is more conservative but it is generally better to preserve deduplication than to maximally optimize every instance. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-09Make StageOption Unserializable (#1891)Jack Koenig
These options are generally specific to a stage and thus should not be propagating across serialization
2020-09-09Loosen inlining restrictions (#1882)Albert Chen
* test multiinfo comparison and mux cond inlining * loosen inlining conditions * fix typo * include dshlw * fix test
2020-09-06Add --pretty:no-expr-inlining to prevent expression inlining (#1869)Jack Koenig
Also rename --Wno-scala-version-warning to --warn:no-scala-version-deprecation and adopt naming convention where resulting annotation matches the CLI option
2020-09-06Support binary files in CustomFileEmission (#1887)Jack Koenig
2020-09-05Better error messages for unserializable annotations (#1885)Jack Koenig
2020-09-04Add test for mem port clock legalizationAlbert Magyar
2020-09-04Legalize memory port clocksAlbert Magyar
2020-09-01InlineBooleanExpressions: test DontTouch (#1880)Albert Chen
* InlineBooleanExpressions: test DontTouch * run scalafmt
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-28Add test for InlineBooleanExpressions add-not exampleAlbert Magyar
2020-08-28Restrict boolean inlining to avoid context-sensitive width bugsAlbert Magyar
* Restore depth-agnostic inlining for simple 'lhs = ref' bool assignments * Address review comments * Run scalafmt
2020-08-28Add custom transforms 'upstream' of emitter annotation in equiv testsAlbert Magyar
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
* FlattenSpec: flattening a module with no instaces should be a no-op * Fix problem when flattening/inlining a lone module Fix an edge case bug in InlineInstances where a circuit containing a lone module is flattened/inlined. This now properly special cases the situation of an empty indexMap which before had to be of length >= 1. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify rename logic in InlineInstances Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Mea culpa Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-08-28Deprecate CompilerAnnotation (#1870)Schuyler Eldridge
* CompilerAnnotation$ emits RunFirrtlTransform Change the CompilerAnnotation object to emit RunFirrtlTransformAnnotations containing the associated emitter. This requires a fix in the Driver compatibility layer to know how to enable one-file-per module emission if either a CompilerAnnotation or a RunFirrtlTransformAnnotation(_: Emitter) is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add ConvertCompilerAnnotation phase Add a phase, ConvertCompilerAnnotation, that converts a CompilerAnnotation to a RunFirrtlTransformAnnotation. This provides a warning to the user if this path is taken. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test of ConvertCompilerAnnotation Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Deprecate CompilerAnnotation$, move helper methods Deprecate the CompilerAnnotation companion object and move it's private utility inside the RunFirrtlTransformAnnotation companion object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Make ConvertCompilerAnnotations private[firrtl] Make this phase private to avoid adding a deprecation warning. Also, remove an unused string value. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix incorrect string in test Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add test that '-X verilog', no emitter yields file Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 10:33:30 +0000