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2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
non-referenced declarations that are not instances, but it doesn't work right now.
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
Conflicts: src/main/stanza/firrtl-ir.stanza src/main/stanza/passes.stanza src/main/stanza/verilog.stanza
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-14Fixed bug in lowering, where the indexes to many-connects and accessors ↵azidar
weren't lowered
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-10Added clock supportazidar
2015-07-07Updated flo backendazidar
2015-07-07Passes riscv-mini testsazidar
2015-07-07Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-06Still partial commit, many tests pass. Many tests fail.azidar
2015-07-06Partial commitazidar
2015-07-06In progress commitazidar
2015-07-06Updated todoazidar
2015-07-02Added firrtl-lexerazidar
2015-07-02Fixed performance bugs, runs 7x fasterazidar
2015-07-02Fixed stanza, optimize works, added a time printoutazidar
2015-07-02Hopefully fixed stanza so it can correctly compile itselfazidar
2015-07-01Updated TODO.azidar
2015-06-12Major revisions to spec. Bumped to v0.1.2azidar
2015-06-05Added updated stanzaazidar
2015-06-05Commited most recent pdfazidar
2015-06-04Fixed fir files so they correctly compile to verilog! Front-end needs to ↵azidar
generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-04Added Adam's changes to stanzaazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Added low firrtl check. Corrected bug in prefix matching in high firrtl checkazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵azidar
low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-06-02turn off eliminate-temps until improvedjackbackrack
2015-06-02merge + fix trim to use correct bits operandsjackbackrack
2015-05-29fix concat, as-sint, turn off temp-eliminationjackbackrack
2015-05-29Fixed bugs in when-coverage pass. Works but has not been thoroughly testedazidar
2015-05-29Added new stanzaazidar
2015-05-29Added custom pass. Does not correctly run, stanza just spins. Requires ↵azidar
debugging.
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
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