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SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
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* Added Zero width wires.
Semantics:
- No change to width inference rules, e.g.
a<0> + b<2> = c<3>
- Replace zero width wires with UInt<1>(0) or SInt<1>(0)
- Performs constant prop.
- Redo width/type inference
* Remove errant println
* Moved ZeroWidth after ConvertFixedToSInt
* Added more tests, bugfix match on connect
Also replaced constprop with infertypes for correctness
* Updated to new emitter and test infrastructure
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Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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Workaround for #470. This allows parsing DoubleLits in subfield
expressions.
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* castrhs shouldn't assume rhs is uint
* don't cast if types are the same
* changed castrhs to catch invalid lhs, rhs type combinations
* change error msg
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update uses
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Also remove parsing support for ids with characters not supported in
Verilog nor in the Firrtl spec
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The fix for PR #305 caused a new compile warning from Cadence Incisive:
always @(*) begin end
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ncelab: *W,STARMT (../TestHarness.MyConfig.v,196147|9): This @* expands to empty list, will never wake up.
This change satisfies all of: VCS, Incisive, Questa, Vivado, Verilator.
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This allows the replseqmem transform to not deduplicate
some memories, based on their name.
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Also add support for width inference
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This comment causes vcs to treat this as a spare memory,
so it will dynamically allocate the required memory, and can
support very large reg constructs this way. This is useful for
test bench memories that might be simulating back DRAM or the like.
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* Rework Attach to work on arbitrary Analog hierarchies
If there are zero or one Analog sources in an Attach (source meaning
wire or parent module port), then the Attach will be emitted as a simple
point to point connection. In the general case, alias is used for
simulation while forwards and backwards assigns for synthesis. Verilator
does not currently support the general case so an `ifdef Verilator
`error is emitted.
* Add helper functions for creating WRef from Reg and Wire
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This fixes an issue I was having with my ClockListAnnotations being duplicated.
h/t @azidar
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Fixes ucb-bar/chisel3#420
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* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests
* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
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This is similar to pr #392 - fetch the resource as a resource, not as a random file otherwise the test will fail if it is executed anywhere outside of the actual source directory.
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Will place tests in ./test_run_dir/ instead of /tmp/
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* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory
* A little bit of style cleanup
* A little bit of style cleanup
* Fix the driver, wasn't appending targetDir properly
Add some docs
* test had wrong value now that targetdir is added to annnos
* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line
* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there
* targetDir annotation is targeted to a CircuitName("All")
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* type conversions between sint/fixed and uint added at memory interfaces for replseqmem
* turns out asFixed requires bp as constant in PrimOps (really should be documented)
* fixed legalizeconnects to handle FixedPt
* added tests for replseqmem failure with signed types
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* Move BackendCompilationUtilities into a util package for use by chisel3.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
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Add a test for cmem and smem with fixed point numbers
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