sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-02-24	Make rocket.fir regression test fail nicer on console	jackkoenig

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
2015-02-18	Added more testing infrastructre, and Makefile to build firrtl	azidar

2015-02-18	Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of ↵	azidar
	IR to match parser.
2015-02-13	First commit.	azidar
	Added stanza as a .zip, changed names from ch to firrtl, and spec.tex is included. need to add installation instructions. TODO's included in README