sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-04-09	Adds check for type of DefRegister initialization	jackkoenig
	Fixes #89
2016-04-09	Fix bundle type equality	Adam Izraelevitz
	Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.
2016-04-08	Fixed bug in Remove Accesses where a WSubAccess's index was not checked for ↵	Adam Izraelevitz
	accesses. Fixes #105
2016-04-08	Add small test for issue #105	jackkoenig

2016-03-15	Revamp string literal handling	jackkoenig

2016-03-10	Add support for right shift by amount larger than argument width	jackkoenig

2016-03-03	Add some integration tests: successful compilation and execution	jackkoenig

2016-02-25	Remove brittle rocket comparison to expected verilog test.	jackkoenig

2016-02-24	Make rocket.fir regression test fail nicer on console	jackkoenig

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
2015-02-18	Added more testing infrastructre, and Makefile to build firrtl	azidar

2015-02-18	Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of ↵	azidar
	IR to match parser.
2015-02-13	First commit.	azidar
	Added stanza as a .zip, changed names from ch to firrtl, and spec.tex is included. need to add installation instructions. TODO's included in README