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2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Add test cases for illegal casts to AsyncReset / ClockAlbert Magyar
2020-04-20Remove repetitive pass lists from WidthTestsAlbert Magyar
2020-04-20Avoid casting 2-bit interval to AsyncReset in testAlbert Magyar
2020-04-14Add Paul's async-reset self-init case as a testAlbert Magyar
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Add test-case for explicit padding of SInts in mverilog compilerAlbert Magyar
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Add test of mixing -e with -E in FirrtlMainSpecSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
* EliminateTargetPaths: add lone instance test cases * EliminateTargetPaths: don't rename lone instances * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Add ground type serializer (#1502)Albert Chen
* update JsonProtocolSpec to test GroundType * add custom serializer for GroundType * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
* Fix dynamic SubAccess of zero-length vectors * Fixes #230 * Add new ZeroLengthVecs pass that occurs before RemoveAccesses * Include this in stage.Forms.MidForm * Add to High->Mid order in compiler test based on @seldridge feedback * Use validif to produce out-of-bounds value in ZeroLengthVecs * Update scaladoc * Fix test imports
2020-04-06Remove deprecated ResolveGenders and CheckGendersAlbert Magyar
* Remove few remaining uses of these passes from FIRRTL codebase
2020-03-30Add previously failing pad(cast(lit)) example as a test caseAlbert Magyar
* Previously, this test failed whenever InlineCasts was run
2020-03-30Port FirrtlRunners.firrtlEquivalenceTest to use FirrtlStageAlbert Magyar
* Make RenameTop DependencyAPI-compliant
2020-03-26Support octal and binary literal formats as described in the specAlbert Magyar
* Fixes #1464
2020-03-25Update scalatest 3.1.0 (#1383)Jim Lawson
* Removed unused imports in src/test/ * Update ScalaTest deprecations. * Update scalatest from 3.0.8 to 3.1.0; apply auto fix for deprecations Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-16Check for collision of defnames with Module namesAlbert Magyar
* Fixes #1096
2020-03-16Check for module name conflictsAlbert Magyar
* Fixes #1436
2020-03-13Make InlineInstances invalidate ResolveKindsJack Koenig
Fixes #1453
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
Introduce Preset Register Specialized Emission - Introduce EmissionOption trait - Introduce PresetAnnotation & PresetRegAnnotation - Enable the collection of Annotations in the Emitter - Introduce collection mechanism for EmissionOptions in the Emitter - Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved) - Add corresponding tests spec and tester Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-12Add out-of-bounds literal access test for ReplaceAccessesAlbert Magyar
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
* Fixes #1214 Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
* Provide an annotation mix-in that marks RTs as dontTouch * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/test/scala/firrtlTests/DCETests.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala * Update OptimizationAnnotations.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-07Add firrtl-json serializers (#1430)Adam Izraelevitz
* Add firrtl-json serializers * Added support for ports, info. Added docs and tests
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
* Avoid IndexOutOfBoundsException when Bits has too few consts * Check for negative consts in all relevant primops * Use BigInt for all checks on primop constants
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
2020-03-02Remove new unreachables in EliminateTargetPathsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add optionalPrerequisites to Dependency APISchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add dependency prettyPrint, visualization updatesSchuyler Eldridge
This adds a prettyPrint method to the DependencyManager to enable textual visualization of the TransformLikes that a DependencyManager determines need to be run. This also cleans up the GraphViz visualization with better edge coloring and now uses the `name` method when labeling graphviz nodes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add additional PhaseManager testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Support Singleton Dependencies (#1275)Albert Magyar
This makes a change to the Dependency API that breaks chisel3. This needs to [skip chisel tests], but is fixed with https://github.com/freechipsproject/chisel3/pull/1270. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-18Add test case for reachableFrom behavior w.r.t. including rootAlbert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
This reverts commit eabc38559b7634ff7147aa0ab3d71e78558d5162.
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
* Revert "Infer resets last connect semantics (#1291)" * Fix handling of invalidated and undriven components of type Reset * Run CheckTypes after InferResets * Make reset inference bidirectional on connect * Support AsyncResetType in RemoveValidIf * Fix InferResets for parent constraints on child ports * Apply suggestions from code review * Add ScalaDoc to InferResets Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
* Add SimplifyBinaryOp trait * Add extra functionality to comparison folding * Add tests * Fix comments from review
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
* Consume NoDedupMemAnnotations in ResolveMemoryReference The ComponentName being pointed to by the annotation no longer exists after ReplaceSeqMems so we should consume the annotations * Support renaming in ReplaceMemMacros Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Add InstanceGraph.staticInstanceCount testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
* Generates lint-clean Verilog for the case: x + -1 ...where x is anything and 1 is any literal. Master behavior: input x : SInt<8> output z : SInt<9> z <= add(x, SInt(-2)) generates assign z = $signed(x) + -8'sh2; After this PR: assign z = $signed(x) - 8'sh2; If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction. Input: input x : SInt<2> output z : SInt<3> z <= add(x, SInt(-2)) now generates (after this PR) assign z = $signed(x) - 3'sh2; * Updated documentation * Change ArrayBuffer to ListBuffer * Change name to minNegValue * Remove mutable public interfaces Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
Add a test that EliminateTargetPaths properly duplicates an annotation pointing at a ModuleTarget. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
* Fixes #1240 * Add failing reg const prop test case from #1240
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
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