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2021-12-18Fix width of signed addition when input to mux (#2440)Jack Koenig
Fix bugs related to arithmetic ops inlined into a mux leg. Add formal equivalence checks to lock in this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
* Add renamemap.MutableRenameMap which includes these methods without deprecation * Deprecate Stringly typed RenameMap APIs which were accidentally undeprecated a while ago Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-12-17Remove some printlns in tests (#2445)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-12-17Modify and optimize performance of propagate annotations (#2393)Jack Koenig
* Change AnnotationSeq underlying from List to Seq It was nothing but pointless copying. * Make propagateAnnotations faster There was lots of expensive logic for very little benefit.
2021-12-13Implement CustomRadixTransform for wave viewers (#2434)Jiuyang Liu
1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix. 2. Add CustomRadixConfigFileAnnotation to output a JSON config file so users can generate scripts on their own. Reviewed-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-30[deprecation clean up] remove trait firrtl.util.BackendCompilationUtilities ↵Jiuyang Liu
(#2423) Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-29[deprecation clean up] remove firrtl.ExecutionOptionsManager (#2422)Jiuyang Liu
Also remove all related APIs: ComposableOptions HasParser CommonOptions HasCommonOptions FirrtlExecutionOptions HasFirrtlOptions FirrtlExecutionResult FirrtlExecutionSuccess FirrtlExecutionFailure ExecutionOptionsManager firrtl.stage.DriverCompatibility.firrtlResultView logger.Logger.makeScope OutputConfig SingleFile OneFilePerModule * Change default LogLevel to None which means "unset" Logger.getGlobalLevel then returns LogLevel.Warn when the current value is LogLevel.None. This preserves the behavior of the default being "Warn" but now uses LogLevel.None to indicate "I'm not setting the value." This resolves issues where it was not possible to tell if annotations were actually setting the log level or if the default level of warn was just being filled in. Co-authored-by: sinofp <sinofp@tuta.io> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-23fix tests that depend on Driver (#2429)Jiuyang Liu
Co-authored-by: sinofp <sinofp@tuta.io>
2021-11-19Disable random init (#2396)Jiuyang Liu
* Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in>
2021-11-12Let firrtl based applications run despite loading unknown annotations (#2387)Chick Markley
An application like barstools may contain a main that loads an annotations file containing annotation classes that are not on it's classpath. This change allows unknown annotations to be preserved by wrapping them in a UnrecognizedAnnotation. If annotations are then output to a file, they will be unwrapped during serialization This feature can be enabled via an AllowUnrecognizedAnnotations annotation Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-10smt: fix handling of div primitive in formal backend (#2409)Kevin Laeufer
We never tested the case where the width of the numerator was less than the denominator. This should fix any issue with this combination.
2021-11-04BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)Kevin Laeufer
2021-10-19Remove The WriteEmitted Phase (#2390)David Biancolin
2021-10-09Support parsing missing keywords as ids (#2381)Jack Koenig
Reset, AsyncReset, Interval, attach, assert, assume, and cover have all been added as keywords but not added to the allowlist for parsing as ids.
2021-10-04Add test of #2379 issue, NFCSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-29TopWiring: filter out unnamed declarations when building source lists (#2376)David Biancolin
* Demonstrate a couple failing cases * Have TopWiring ignore unnamed declarations as potential sources
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
* Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells.
2021-09-23transforms.formal: ensure named statements as output (#2367)Kevin Laeufer
2021-09-14Fix multi-protobuf test when run multiple times (#2357)Jack Koenig
The test was leaving the test directory in a dirty state that would fail on a rerun. Fix the test so that it can be run multiple times in a row.
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-09-08smt: refactor SMT expression library (#2347)Kevin Laeufer
2021-09-08Multi protobuf module emission and consumption (#2344)Jared Barocsi
* Add compiler option (`-p`) to emit individual module protobufs * Implement multi module combination when reading directory of protobufs Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-30[smt] treat stop with non-zero ret like an assertion (#2338)Kevin Laeufer
We treat it as an assertion that the stop will never be enabled. stop(0) will still be ignored (but now demoted to a info from a warning).
2021-08-26Fix dshl zero-width shift behavior (#2339)Schuyler Eldridge
* Fix dshl zero-width shift behavior Add a special case for dshl handling in the ZeroWidths pass. If one expression is shifted by a second, zero-width expression, just return the first expression. This prevents a bug where the width will incorrectly expand due to zero-widths introducing a 1-bit zero expression. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix dshl zero-width shift behavior
2021-08-21Add BufferedCustomFileEmission (#2334)Jack Koenig
Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize file emission.
2021-08-20Fix Serializer for single indented DefModule emission (#2332)Jack Koenig
2021-08-10[smt] make SMTLib + Btor2 emitters public objects (#2326)Kevin Laeufer
This will make it easier for formal verification libraries to make use of these emitters.
2021-08-10[smt] PropagatePresetAnnotations is now a real prereq (#2325)Kevin Laeufer
2021-08-02remove LoweringCompilersSpec (#2310)Kevin Laeufer
This has outlived its usefulness.
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-29Dedup attribute annos (#2297)Jared Barocsi
* Add new util "groupByIntoSeq" * Restore annotation order when dedupping annotations * Attribute annotations now deduplicate * Implement doc string anno dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-27ir: make HashCode.toHashString public (#2302)Kevin Laeufer
This will allow chiseltest to save the hash code to disk for the purpose of caching simulation binaries.
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
* Add transform to deduplicate memory annotations * Add annotation deduplication to Dedup stage * ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform * Verilog emitter now throws exception when memory annotations fail to dedup Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-07Replace hard coded line separators with system specific ones (#2281)Boyang Han
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
2021-06-18Fix MultiInfo parser + serialization bug (#2265)Jared Barocsi
* Restore parsed MultiInfo structure in firrtl parser * Change erroneous expected output in InfoSpec test FileInfo compression sorts the outputted entries alphabetically, but this test did not reflect that fact * Fix typo in comment * Add unit tests for file locator parsing * Fix syntax issues and typos * More redundant braces removed Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-17smt: include firrtl statement names in SMT and btor2 output (#2270)Kevin Laeufer
* smt: include firrtl statement names in SMT and btor2 output * smt: remove println * smt: make tests run again and fix stale ones Apparently `private` classes aren't found by th sbt test runner.
2021-06-17Add --start-from option (#2273)Schuyler Eldridge
Add a new option to the FIRRTL compiler, "--start-from = <form>". If used, this will cause the compiler to assume that the input FIRRTL circuit is already in the specific form. It will then skip unnecessary passes given this information. E.g., if a user requests to run "firrtl -X verilog --start-from low" then the compiler will only run transforms necessary to get from low FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be run if needed (checks and type/kind/flow resolution). To implement this, a CurrentFirrtlStateAnnotation is added. Advanced users can use this directly to tell the FIRRTL compiler exactly what transforms have already been run, including the ability to ignore checks or type/kind/flow resolution if they so desire. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-17Add Protocol Buffer emission (#2271)Schuyler Eldridge
* Add Protocol Buffer emission export This adds infrastructure and annotations that let a user emit a FIRRTL circuit as a Protocol Buffer. Fixes #1696. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add Protocol Buffer emission export
2021-06-15make PresetRegAnnotation public (#2254)Kevin Laeufer
* make PresetRegAnnotation public this annotation is useful outside the firrtl compiler: - to implement a pass that creates registers which need to be initialized at the beginning of simulation (e.g., for formal verification) - to support preset registers in treadle * add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
2021-06-14Add -X mhigh compiler for minimal high form (#2268)Schuyler Eldridge
Add a compiler/emitter that can target minimal high form. This will produce output that only has CHIRRTL constructs removed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-03Replace mem macros renaming (#2243)Albert Chen
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen * Add CLI support for GenVerilogMemBehaviorModelAnno * Add simple test for GenVerilogMemBehaviorModelAnno * Fix for review 1. rename case class Port(prefix, `type`) to Port(prefix, portType) 2. fix AnnotatedMemoriesAnnotation collect function. 3. fix bug that ModuleName is not correct. * Format DumpMemoryAnnotations & ReplSeqMemTests * Fix for review 1. Inline genDecl, genPortSpec, genSequential, genCombinational 2. Add DefAnnotatedMemory informations in header 3. Change helpText 4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog * Fix ReadWritePort mask name Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21Optimize Annotation.getTargets (#2244)Jack Koenig
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
* add more inline renaming test cases * InlineInstances: fix renaming for local targets * run scalafmt Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
LowerTypes creates a lot of mappings for the RenameMap. The built-in .distinct of renames becomes a performance program for designs with deeply nested Aggregates. Because LowerTypes does not create duplicate renames, it can safely eschew the safety of using .distinct via a private internal API.
2021-05-17Use os-lib to rewrite Z3ModelChecker (#2223)Jiuyang Liu
* add os-lib to dependency. * use os-lib in Z3ModelChecker * fix for review by Kevin.
2021-05-14Add JsonProtocol.serializeRecover (#2227)Jack Koenig
This function will safely wrap any unserializeable annotations in UnserializeableAnnotations so that they can be safely serialized to JSON for logging.
2021-05-13Implement MFC-style source locator compression (#2212)Jared Barocsi
* Implement MFC-style source locator compression * Fix formatting issues * Fix emitting empty FileInfo if the firrtl doesn't have one * Remove '.scala' requirement in FileInfo parsing regex * Handle parsing of FileInfos with no line/col nums * Split FileInfos only if they match This should fix any issues with FileInfos that do not use the "file line:col" format, and allow any valid firrtl using these info comments to compile. * Add unit tests for locator compression * Move InfoTests to InfoSpec class * Fix existing unit tests with fileinfo comments * Add unit tests to ignore the algorithm's own output
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