| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-26 | add CInferMDirSpec | Donggyu Kim | |
| 2016-09-26 | Added max width check to dshl shift amount (#318) | Adam Izraelevitz | |
| Address #297 | |||
| 2016-09-25 | Spec features added: AnalogType and Attach (#295) | Adam Izraelevitz | |
| * Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes | |||
| 2016-09-22 | Fixed width inference for add, sub (#312) | Adam Izraelevitz | |
| Fixes #308 Fixes #193 | |||
| 2016-09-21 | Fix clock connections in InferReadWrite (#310) | Donggyu | |
| 2016-09-21 | refactor AnnotateMemMacros | Donggyu Kim | |
| 2016-09-21 | refactor InferReadWrite | Donggyu Kim | |
| 2016-09-14 | Added Rob.fir for regression testing (#258) | Donggyu | |
| 2016-09-14 | fix enable signal inferecne for smems' read ports (#289) | Donggyu | |
| 2016-09-14 | Fixed infinite loop for finding connect origin in ReplSeqMem (#300) | Angie Wang | |
| * Addressed the fact that a node can be connected to itself (updating reg) | |||
| 2016-09-12 | Add LegalizeSpec for testing Verilog Legalization pass | Jack | |
| 2016-09-12 | Added test to check invalid bug was fixed | azidar | |
| 2016-09-12 | Bug fix -- remove all empty expressions after ReplSeqMem passes (#294) | Angie Wang | |
| * Bug fix -- remove all empty expressions after ReplSeqMem passes * Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage) | |||
| 2016-09-08 | Remove brittle ReplSeqMemTest | jackkoenig | |
| This test is breaks with any minor change to code generation. It should be replaced with a more robust test. | |||
| 2016-09-08 | remove Utils.{AND, OR, NOT, EQV} | Donggyu Kim | |
| hidden const props not desirable | |||
| 2016-09-08 | clean up ExpandWhens | Donggyu Kim | |
| 2016-09-07 | refactor checks | Donggyu Kim | |
| 2016-09-06 | Address style feedback and add tests for getConnectOrigin utility | Angie | |
| 2016-09-06 | Expanded annotations for valid memory sizes | Angie | |
| 2016-09-06 | Added simple unit test for ReplSeqMem | Angie | |
| 2016-08-25 | emit wires instead of registers for invalid randomization | Howard Mao | |
| Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires. | |||
| 2016-08-25 | update verilog generation test | Howard Mao | |
| 2016-08-16 | add test case for clock type connection (#239) | mwachs5 | |
| 2016-08-04 | Addd check: bits, tail, head arg width | azidar | |
| 2016-08-03 | fixes small mistakes in serialize (#216) | Donggyu | |
| 2016-08-02 | Merge pull request #203 from ucb-bar/fix_mem_infer | Adam Izraelevitz | |
| Fix mem infer | |||
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim | |
| turned on with '--inferRW <circuit name>' | |||
| 2016-08-02 | Merge pull request #214 from ucb-bar/fix-thread-unsafety | Adam Izraelevitz | |
| Fix use of global state in instance loop checking | |||
| 2016-08-02 | Merge pull request #211 from ucb-bar/fix-subaccess | Adam Izraelevitz | |
| Refactor RemoveAccesses and fix bug #210. | |||
| 2016-08-02 | Fix use of global state in instance loop checking | jackkoenig | |
| Also increase sensitivity of thread safety checking Fixes #159 | |||
| 2016-08-01 | Refactor RemoveAccesses and fix bug #210. | azidar | |
| Added corresponding unit test. | |||
| 2016-08-01 | Fix StringSpec generators to only choose from valid values. | Jack Koenig | |
| The old almost equivalent syntax gives the same result but can cause the test to fail if too many invalid values are thrown away. | |||
| 2016-07-27 | Fixed compilation error using old annotations | azidar | |
| 2016-07-27 | Reworked annotation system. Added tenacity and permissibility | Adam Izraelevitz | |
| Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala | |||
| 2016-07-27 | Merge pull request #198 from ucb-bar/add-chirrtl-check | Adam Izraelevitz | |
| Added a Chirrtl check for undeclared wires, etc. | |||
| 2016-07-25 | Detects and flags cyclic module loops | chick | |
| 2016-07-21 | Added a Chirrtl check for undeclared wires, etc. | azidar | |
| 2016-06-10 | API Cleanup - AST | Jack | |
| trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._ | |||
| 2016-06-10 | Add test to check compiler is thread safe | Jack Koenig | |
| 2016-05-24 | Added Errors class and fixed tests. | azidar | |
| Canonicalizes catching/throwing PassExceptions. | |||
| 2016-05-24 | add better type mismatch error message | Colin Schmidt | |
| also check for it int unittest | |||
| 2016-05-24 | Add integration test for single-ported memory | jackkoenig | |
| 2016-05-12 | Restructured Compiler to use Transforms. Added an InlineInstance pass. | Adam Izraelevitz | |
| Transforms are new unit of modularity within the compiler. | |||
| 2016-05-12 | Implement File Info | jackkoenig | |
| 2016-05-10 | Add test suite for Constant Propagation | Adam Izraelevitz | |
| Add unit tests for splitting expressions and padding widths | |||
| 2016-05-03 | Add Tests for Check Initialization | Adam Izraelevitz | |
| 2016-05-03 | Add Expand Whens test | jackkoenig | |
| 2016-04-26 | Test that nested expressions don't make it to the Emitter | Andrew Waterman | |
| 2016-04-26 | Fixed the check for bundle equality to allow relative flips to be wrong, but ↵ | Adam Izraelevitz | |
| the leaf directions are the same | |||
| 2016-04-26 | Add test for recursive check for whether BundleType contains flips | Adam Izraelevitz | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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