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Constant Propagation will not optimize across components marked
dontTouch
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This makes it more concise to write tests
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Gives all transform specs access to useful utilities (like dontTouch).
Deletes some duplicate code. Parsing mode UseInfo is fine for
everything, only matters if the test actually uses info.
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Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.
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This requires a quick second pass to back propagate constant wires but
the QoR win is substantial. We also only need to count back propagations
in determining whether to run ConstProp again which shaves off an
iteration in the common case.
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Also add tests for what should happen to 'is invalid' in ExpandWhens
Fixes #606
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Resolves #600
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* Update dependencies and JavaConverters for Scala 2.12
* Bump Scala (and library) version(s).
* replace "error" with "Utils.error"; bump Scala version to 2.11.11
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* Upgrade Logging facility
Make thread-safe
Make logging by package name work
Use caching of class names to level for performance
Make some tests to show this working
* quick fix for dynamic logging variable
* A number of changes based on Adam's suggestions
Default LoggerState
But there is an invoke method now to handle threading issues. This should be propagated to other
projects Driver.execute methods
* Add built-in support for string capture of Logging
* Usability fixes for logging stuff. Settings made to the logger prior to execute/invoke will be passed along if possible.
* A couple style fixes
Comment and privatize Logger state
* Name and save string buffers used for logging
* Fix default logging state setting
Fix logging test, did not have change to command argument
* comment out logging in InlineInstanceTests
* Changed invoke to makeScope
Nested makeScopes share same state object
Removed earlier named string buffer implementation
* Better name for captor get data
* Add trace tests to make sure it works too
* Fix call into logger settings
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Fixes #589
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Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.
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* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
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Remove infix notation on calls with side effects.
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Test for #468
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Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
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Also add GlobalCircuitAnnotation for creating similar annotations
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Now remove DefNodes of zero width
Don't deeply walk nodes (was the source of the bug)
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SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
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* Added Zero width wires.
Semantics:
- No change to width inference rules, e.g.
a<0> + b<2> = c<3>
- Replace zero width wires with UInt<1>(0) or SInt<1>(0)
- Performs constant prop.
- Redo width/type inference
* Remove errant println
* Moved ZeroWidth after ConvertFixedToSInt
* Added more tests, bugfix match on connect
Also replaced constprop with infertypes for correctness
* Updated to new emitter and test infrastructure
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Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
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Changes Emitters to also be Transforms and use Annotations for both
telling an emitter to do emission as well as getting the emitted result.
Helper functions ease the use of the new interface. Also adds a
FirrtlExecutionOptions field as well as a command-line option. Use of
Writers in Compilers and Emitters is now deprecated.
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Workaround for #470. This allows parsing DoubleLits in subfield
expressions.
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Also remove parsing support for ids with characters not supported in
Verilog nor in the Firrtl spec
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This allows the replseqmem transform to not deduplicate
some memories, based on their name.
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Also add support for width inference
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