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- Fix & test MemorySynthInit behavior with MemoryArrayInitAnnotation and MemoryScalarInitAnnotation.
Add test case for MemoryRandomInitAnnotation which is, on the contrary, expected not to leak any randomization statement in synthesis context.
- Refactor MemoryInitSpec for improved results readability
Context:
PR #2166 (commit: 4530152) introduced MemorySynthInit annotation to control whether statement generated with Memory*InitAnnotation (emitted within initial begin block in verilog) should be guarded with ifndef SYNTHESIS or not.
Unfortunately only one configuration (MemoryFileInlineAnnotation) has been tested while the others have been generating incorrect verilog statements (MemoryArrayInitAnnotation and MemoryScalarInitAnnotation).
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
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Verification statements are guarded by reset.
If this reset happens to be a "preset" type
reset, they should always be active.
The easiest way to achieve that is to replace
all uses of "preset" resets with zero.
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* Add FileInfo to asyncResetAlwaysBlocks
Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).
RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.
Async always blocks don't provide their only FileInfo, so there are no line numbers.
This commit gives async always block the extra FileInfo to show line numbers for them.
This code:
```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission
class Test extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val valid = RegInit(false.B)
valid := io.in
io.out := valid
}
object Test extends App {
new ChiselStage().execute(Array(), Seq(
ChiselGeneratorAnnotation(() => new Test()),
CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
))
}
```
will generate this Verilog:
```verilog
module Test(
input clock,
input reset,
input io_in,
output io_out
);
reg valid; // @[Playground.scala 10:22]
assign io_out = valid; // @[Playground.scala 12:10]
always @(posedge clock or posedge reset) begin
if (reset) begin // @[Playground.scala 10:22]
valid <= 1'h0; // @[Playground.scala 10:22]
end else begin
valid <= io_in; // @[Playground.scala 11:9]
end
end
endmodule
```
they have correct line numbers (10, 10, 11).
* Add test for async always block line numbers
* Add comment for review
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Fix bugs related to arithmetic ops inlined into a mux leg. Add formal
equivalence checks to lock in this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add renamemap.MutableRenameMap which includes these methods without
deprecation
* Deprecate Stringly typed RenameMap APIs which were accidentally
undeprecated a while ago
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Change AnnotationSeq underlying from List to Seq
It was nothing but pointless copying.
* Make propagateAnnotations faster
There was lots of expensive logic for very little benefit.
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1. Add CustomRadix{Def,Apply}Annotation to define and apply custom radix.
2. Add CustomRadixConfigFileAnnotation to output a JSON config file so
users can generate scripts on their own.
Reviewed-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: sinofp <sinofp@tuta.io>
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(#2423)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Also remove all related APIs:
ComposableOptions
HasParser
CommonOptions
HasCommonOptions
FirrtlExecutionOptions
HasFirrtlOptions
FirrtlExecutionResult
FirrtlExecutionSuccess
FirrtlExecutionFailure
ExecutionOptionsManager
firrtl.stage.DriverCompatibility.firrtlResultView
logger.Logger.makeScope
OutputConfig
SingleFile
OneFilePerModule
* Change default LogLevel to None which means "unset"
Logger.getGlobalLevel then returns LogLevel.Warn when the current value
is LogLevel.None. This preserves the behavior of the default being
"Warn" but now uses LogLevel.None to indicate "I'm not setting the
value." This resolves issues where it was not possible to tell if
annotations were actually setting the log level or if the default level
of warn was just being filled in.
Co-authored-by: sinofp <sinofp@tuta.io>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: sinofp <sinofp@tuta.io>
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* Add option to disable random mem/reg init
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
* fix for code review.
Co-authored-by: SharzyL <me@sharzy.in>
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An application like barstools may contain a main that loads an annotations file containing
annotation classes that are not on it's classpath. This change allows unknown annotations
to be preserved by wrapping them in a UnrecognizedAnnotation. If annotations are then output
to a file, they will be unwrapped during serialization
This feature can be enabled via an AllowUnrecognizedAnnotations annotation
Co-authored-by: chick <chick.markley@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Reset, AsyncReset, Interval, attach, assert, assume, and cover have all
been added as keywords but not added to the allowlist for parsing as
ids.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Demonstrate a couple failing cases
* Have TopWiring ignore unnamed declarations as potential sources
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The test was leaving the test directory in a dirty state that would fail
on a rerun. Fix the test so that it can be run multiple times in a row.
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BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
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* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Fix dshl zero-width shift behavior
Add a special case for dshl handling in the ZeroWidths pass. If one
expression is shifted by a second, zero-width expression, just return
the first expression. This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix dshl zero-width shift behavior
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Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.
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This has outlived its usefulness.
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
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* Restore parsed MultiInfo structure in firrtl parser
* Change erroneous expected output in InfoSpec test
FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact
* Fix typo in comment
* Add unit tests for file locator parsing
* Fix syntax issues and typos
* More redundant braces removed
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Add Protocol Buffer emission export
This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.
Fixes #1696.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add Protocol Buffer emission export
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* make PresetRegAnnotation public
this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
need to be initialized at the beginning of simulation
(e.g., for formal verification)
- to support preset registers in treadle
* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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Add a compiler/emitter that can target minimal high form. This will
produce output that only has CHIRRTL constructs removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* ReplaceMemMacros: add target rename test case
* ReplaceMemMacros: rename references to instances
* fix renaming for deduped mems
* use grouped DummyAnnos to preserve order
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* run scalafmt
* flatten targets
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add more inline renaming test cases
* InlineInstances: fix renaming for local targets
* run scalafmt
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.
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This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.
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* Implement MFC-style source locator compression
* Fix formatting issues
* Fix emitting empty FileInfo if the firrtl doesn't have one
* Remove '.scala' requirement in FileInfo parsing regex
* Handle parsing of FileInfos with no line/col nums
* Split FileInfos only if they match
This should fix any issues with FileInfos that do not use the "file line:col"
format, and allow any valid firrtl using these info comments to compile.
* Add unit tests for locator compression
* Move InfoTests to InfoSpec class
* Fix existing unit tests with fileinfo comments
* Add unit tests to ignore the algorithm's own output
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* remove all deprecations, switch to new API.
* Add MemLibOutConfigFileAnnotation to replace ConfWriter.
* Inline CreateMemoryAnnotations in ReplSeqMem.
* Dont use ConfWriter anymore.
* Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation.
* Fix for review.
0. Since DependencyAPI only initiate transform only once, ListBuffer is
dangerous to use, remove defAnnotatedMemories from Transform.
1. Add trait HasAnnotatedMemories to store ListBuffer,
MemLibOutConfigFileAnnotation also extends from which now.
* Use two annotations converting and storing DefMemory.
0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation
creating PinAnnotation.
1. add DumpMemoryAnnotations to convert from
AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation
2. refactor MemLibOutConfigFileAnnotation and remove
HasAnnotatedMemories
3. add private AnnotatedMemoriesCollectorAnnotation to store mutable
DefAnnotatedMemory
4. change ReplSeqMem to SeqTransform
* Fix for review.
0. replace AnnotatedMemoriesCollectorAnnotation with immutable
AnnotatedMemoriesAnnotation.
1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute.
* private functions in ReplaceMemMacros transform.
* scalafmt
* remove ConfWriter API.
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* Fixes #2173
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Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
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To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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