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path: root/src/test/scala/firrtlTests/transforms
AgeCommit message (Expand)Author
2020-08-22Async reset tieoff bug (#1854)David Biancolin
2020-08-14All of src/ formatted with scalafmtchick
2020-08-12Combined Uniquify and LowerTypes pass (#1784)Kevin Laeufer
2020-08-11File Serialization of Annotations (#1277)Schuyler Eldridge
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
2020-07-31[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)Jiuyang Liu
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
2020-06-25Test ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
2020-06-25Test ManipulateNamesSpecSchuyler Eldridge
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
2020-06-10Build ArrayBuffers in Block.mapStmt (#1669)Jack Koenig
2020-06-04Add test case for retype-based component renaming in DedupModulesAlbert Magyar
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-03-17[RFC] Factor out common test classes; package them (#1412)David Biancolin
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
2019-09-16Rename gender to flowSchuyler Eldridge
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-07Add tests on RemoveReset of invalid initsSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-01-21Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-04Fix GroupComponents to work with unused componentsJack Koenig
2019-01-02Make GroupComponents run ResolveKindsJack Koenig
2018-12-13[Top Wiring] Expand top wiring to work on aggregatesDavid Biancolin
2018-12-06Fix bug in dedup where lots of annotations could prevent dedup (#958)Jack Koenig
2018-11-15Combine cats (#851)Albert Chen
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
2018-10-30Instance Annotations (#926)Adam Izraelevitz
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
2018-09-07Bug Fixes in TopWiring (#885)alonamid
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