aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/transforms
AgeCommit message (Collapse)Author
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-01-31Blackboxhelper (#418)Chick Markley
* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory * A little bit of style cleanup * A little bit of style cleanup * Fix the driver, wasn't appending targetDir properly Add some docs * test had wrong value now that targetdir is added to annnos * Now saves a list of all black box verilog files moved into target directory. Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line * Made black box source helper be low to low form Added it to the verilog compiler transforms Added a test to make sure it got there * targetDir annotation is targeted to a CircuitName("All")
2017-01-20Remove merging of source locators during module deduplicationJack
2016-12-14Added NoDedup annotation and test (#397)Adam Izraelevitz
2016-11-30Bugfix: Dedup aggressively (ignore comments) (#375)Adam Izraelevitz
FileInfo is merged
2016-11-23Stringified annotations (#367)Adam Izraelevitz
Restricts annotations to be string-based (and thus less typesafe) Makes annotations more easily serializable and interact with Chisel
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Add a pass to deduplicate modulesazidar