sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2020-08-22	Async reset tieoff bug (#1854)	David Biancolin
	* Elide emission of literals for async reset in sensitivity lists * Deprecate LegalizeClocksTransform Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-14	All of src/ formatted with scalafmt	chick

2020-05-13	consolidated wire+assign to just wire, with expression inlined (#1600)	Murali Vijayaraghavan
	* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-17	[RFC] Factor out common test classes; package them (#1412)	David Biancolin
	* Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-01-07	Fix literals cast to Clocks in Print and Stop	Jack Koenig
	Many tools don't except 'always @(posedge 1'h0)' so we assign the literal to a wire and use that as the posedge target.