sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2017-02-14	Fixes #441, ConvertFixedToSInt not recursing exps	Adam Izraelevitz

2017-02-12	Changed fixed-point cat semantics to return uint (#436)	Adam Izraelevitz

2017-01-23	Add FixedType to uniqueify match statement.	Paul Rigge
	Add a test for cmem and smem with fixed point numbers
2016-12-08	Clk2clock - rename the implicit "clk" module input "clock" (#387)	Jim Lawson
	* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-11-23	Stringified annotations (#367)	Adam Izraelevitz
	Restricts annotations to be string-based (and thus less typesafe) Makes annotations more easily serializable and interact with Chisel
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04	Refactor Compilers and Transforms	jackkoenig
	* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-10-30	Cleanup fixed point tests (#339)	Jack Koenig
	Change FixedPointMathSpec tests to use FlatSpec style instead of println Remove other printlns Remove vim comments at end of files
2016-10-17	Add fixed point type (#322)	Adam Izraelevitz
	* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case