| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-05-10 | Update rename2 (#478) | Adam Izraelevitz | |
| * Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check | |||
| 2017-03-29 | Fix bug where zero width expressions in nodes wouldn't get zeroed (#514) | Jack Koenig | |
| 2017-03-22 | Fixed zero width perf bug #502 | Adam Izraelevitz | |
| Now remove DefNodes of zero width Don't deeply walk nodes (was the source of the bug) | |||
| 2017-03-06 | Zero width (#402) | Adam Izraelevitz | |
| * Added Zero width wires. Semantics: - No change to width inference rules, e.g. a<0> + b<2> = c<3> - Replace zero width wires with UInt<1>(0) or SInt<1>(0) - Performs constant prop. - Redo width/type inference * Remove errant println * Moved ZeroWidth after ConvertFixedToSInt * Added more tests, bugfix match on connect Also replaced constprop with infertypes for correctness * Updated to new emitter and test infrastructure | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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