| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-02-22 | Add Width Constraints with Annotations (#956) | Albert Chen |
| 2018-02-27 | Refactor Annotations (#721) | Jack Koenig |
| 2018-02-07 | Fix EulerTour for circuits with one module (#736) | Schuyler Eldridge |
| 2018-01-15 | WiringTransform Refactor (#648) | Schuyler Eldridge |
| 2017-03-22 | Bugfix: apply/unapply of PinAnnotation broken | azidar |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-23 | Stringified annotations (#367) | Adam Izraelevitz |
| 2016-11-15 | Fixed multi wiring (#368) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-27 | Wiring (#348) | Adam Izraelevitz |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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