sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-12-13	Add MaxWidth of 1,000,000 bits	jackkoenig
	Also base max dshl check on MaxWidth instead of just 31 bits Resolves #320
2016-11-09	Bugfix: removed recursive removal in infer widths	azidar
	This will certainly lead to more uninferred width errors, but now widths that were previously incorrectly inferred are now correctly uninferred. An example is: reg r : UInt, clock with: (reset => (reset, UInt<2>(3))) node x = add(r, r) r <= x Here, r's width follows the following formula, which cannot be solved: rWidth >= max(max(rWidth, rWidth) + 1, 2)
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04	Refactor Compilers and Transforms	jackkoenig
	* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-09-26	Added max width check to dshl shift amount (#318)	Adam Izraelevitz
	Address #297
2016-09-22	Fixed width inference for add, sub (#312)	Adam Izraelevitz
	Fixes #308 Fixes #193