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* Changed primops to not accept mixed-type args
* Changed return type of sub of two uints to uint
* Added negative tests
* Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests
* Clarified test description and remove println
* Fixed use of throwInternalError
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Also base max dshl check on MaxWidth instead of just 31 bits
Resolves #320
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This will certainly lead to more uninferred width errors, but now widths
that were previously incorrectly inferred are now correctly uninferred.
An example is:
reg r : UInt, clock with: (reset => (reset, UInt<2>(3)))
node x = add(r, r)
r <= x
Here, r's width follows the following formula, which cannot be solved:
rWidth >= max(max(rWidth, rWidth) + 1, 2)
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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Address #297
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Fixes #308
Fixes #193
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