| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2017-02-26 | Align types and names of ports in emitted Verilog (#463) | Jack Koenig |
| 2017-01-19 | Verilog rem fix (#404) | grebe |
| 2016-11-23 | Stringified annotations (#367) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-31 | Fixed Verilog emission of andr, orr, and xorr (#357) | Adam Izraelevitz |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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