sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-09-08	remove Utils.{AND, OR, NOT, EQV}	Donggyu Kim
	hidden const props not desirable
2016-08-04	Addd check: bits, tail, head arg width	azidar

2016-08-01	Refactor RemoveAccesses and fix bug #210.	azidar
	Added corresponding unit test.
2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-24	Added Errors class and fixed tests.	azidar
	Canonicalizes catching/throwing PassExceptions.
2016-05-24	add better type mismatch error message	Colin Schmidt
	also check for it int unittest
2016-05-12	Implement File Info	jackkoenig

2016-05-10	Add test suite for Constant Propagation	Adam Izraelevitz
	Add unit tests for splitting expressions and padding widths
2016-04-26	Test that nested expressions don't make it to the Emitter	Andrew Waterman

2016-04-26	Fixed the check for bundle equality to allow relative flips to be wrong, but ↵	Adam Izraelevitz
	the leaf directions are the same
2016-04-16	Add license to tests	jackkoenig

2016-04-09	Adds check for type of DefRegister initialization	jackkoenig
	Fixes #89
2016-04-09	Fix bundle type equality	Adam Izraelevitz
	Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.