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path: root/src/test/scala/firrtlTests/UnitTests.scala
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2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
SInt representation is no longer 2's complement, but instead a positive number (hex or base 10) that is optionally preceded by a sign (-+).
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2016-12-08Clk2clock - rename the implicit "clk" module input "clock" (#387)Jim Lawson
* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
Also run CheckTypes after ExpandWhens Fixes #330
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
Prefix temporary names with underscores so Verilator won't trace them Use verilator argument "--trace-underscore" if you want to trace these signals
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
Fixes #329
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-08-04Addd check: bits, tail, head arg widthazidar
2016-08-01Refactor RemoveAccesses and fix bug #210.azidar
Added corresponding unit test.
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-24Added Errors class and fixed tests.azidar
Canonicalizes catching/throwing PassExceptions.
2016-05-24add better type mismatch error messageColin Schmidt
also check for it int unittest
2016-05-12Implement File Infojackkoenig
2016-05-10Add test suite for Constant PropagationAdam Izraelevitz
Add unit tests for splitting expressions and padding widths
2016-04-26Test that nested expressions don't make it to the EmitterAndrew Waterman
2016-04-26Fixed the check for bundle equality to allow relative flips to be wrong, but ↵Adam Izraelevitz
the leaf directions are the same
2016-04-16Add license to testsjackkoenig
2016-04-09Adds check for type of DefRegister initializationjackkoenig
Fixes #89
2016-04-09Fix bundle type equalityAdam Izraelevitz
Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.