| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-03-17 | [RFC] Factor out common test classes; package them (#1412) | David Biancolin | |
| * Pull out common test utilities into a separate package * Project a fat jar for test utilities Co-authored-by: Albert Magyar <albert.magyar@gmail.com> | |||
| 2020-02-12 | Removed unused imports in src/test/ (#1381) | Jim Lawson | |
| Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2018-05-15 | Replace truncating add and sub with addw/subw (#800) | Jack Koenig | |
| Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog. | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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