| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-05-15 | Replace truncating add and sub with addw/subw (#800) | Jack Koenig | |
| Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog. | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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