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path: root/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
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2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-07Fix dynamic SubAccess of zero-length vectors (#1450)Albert Magyar
* Fix dynamic SubAccess of zero-length vectors * Fixes #230 * Add new ZeroLengthVecs pass that occurs before RemoveAccesses * Include this in stage.Forms.MidForm * Add to High->Mid order in compiler test based on @seldridge feedback * Use validif to produce out-of-bounds value in ZeroLengthVecs * Update scaladoc * Fix test imports
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
Introduce Preset Register Specialized Emission - Introduce EmissionOption trait - Introduce PresetAnnotation & PresetRegAnnotation - Enable the collection of Annotations in the Emitter - Introduce collection mechanism for EmissionOptions in the Emitter - Add PropagatePresetAnnotation transform to annotate register for emission and clean-up the useless reset tree (no DCE involved) - Add corresponding tests spec and tester Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>