sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-07-29	RemoveWires: improve dependencies and declare ResolveKinds as an invalidation...	Kevin Laeufer
2020-07-29	InferTypes: fix bugs with unknown widths on ports and memories (#1769)	Kevin Laeufer
2020-07-25	Integrate new transforms with firrtl.stage.Forms (#1754)	Schuyler Eldridge
2020-07-16	Remove overlapping inputForm=LowForm tests	Schuyler Eldridge
2020-06-26	Enable ConvertAsserts in default Verilog compiler	Albert Magyar
2020-06-23	Basic model checking API (#1653)	Tom Alcorn
2020-06-19	RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)	Albert Chen
2020-05-04	Add LegalizeAndReductionsTransform	Jack Koenig
2020-05-01	Add missing invalidations to some transforms (#1541)	Schuyler Eldridge
2020-04-13	Ensure PadWidths is run in mverilog compiler	Albert Magyar
2020-04-07	Fix dynamic SubAccess of zero-length vectors (#1450)	Albert Magyar
2020-03-12	Add Support for FPGA Bitstream Preset-registers (#1050)	John's Brew
2020-03-11	Migrate to DependencyAPI	Schuyler Eldridge