| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-02-21 | Change primop arg type (#587) | Adam Izraelevitz |
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig |
| 2017-04-18 | "Scope" test resource (top.cpp). (#398) | Jim Lawson |
| 2017-03-15 | Use newer rocket regression spec without comb loop | Albert Magyar |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-10-26 | Improve integration test API and add support for Verilog resources | jackkoenig |
| 2016-09-14 | Added Rob.fir for regression testing (#258) | Donggyu |
| 2016-05-24 | Add integration test for single-ported memory | jackkoenig |
| 2016-04-16 | Add license to tests | jackkoenig |
| 2016-03-10 | Add support for right shift by amount larger than argument width | jackkoenig |
| 2016-03-03 | Add some integration tests: successful compilation and execution | jackkoenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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