| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-07-03 | Improve code generation for smem wmode and [w]mask ports (#834) | Andrew Waterman |
| 2018-02-27 | Refactor Annotations (#721) | Jack Koenig |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz |
| 2017-03-09 | make sure infer-rw works for exclusive when statements (#481) | Donggyu |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-23 | Stringified annotations (#367) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-30 | Keep package name + directory structure consistent (#354) | Colin Schmidt |
| 2016-09-21 | Fix clock connections in InferReadWrite (#310) | Donggyu |
| 2016-09-21 | refactor InferReadWrite | Donggyu Kim |
| 2016-08-03 | fixes small mistakes in serialize (#216) | Donggyu |
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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