aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/FirrtlSpec.scala
AgeCommit message (Collapse)Author
2018-02-27Refactor Annotations (#721)Jack Koenig
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
2017-11-08Add FirrtlCheckers and scalatest helpers for testingJack Koenig
2017-06-28[Testing] Have SimpleTransformSpec mix in FirrtlMatchersJack Koenig
Gives all transform specs access to useful utilities (like dontTouch). Deletes some duplicate code. Parsing mode UseInfo is fine for everything, only matters if the test actually uses info.
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation. Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed. This transform preserves deduplication. All instances of a given DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
Will place tests in ./test_run_dir/ instead of /tmp/
2017-01-27Move BackendCompilationUtilities into a util package for use by chisel3. (#400)Jim Lawson
* Move BackendCompilationUtilities into a util package for use by chisel3. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util.
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
Also run CheckTypes after ExpandWhens Fixes #330
2016-11-23Stringified annotations (#367)Adam Izraelevitz
Restricts annotations to be string-based (and thus less typesafe) Makes annotations more easily serializable and interact with Chisel
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04Refactor Compilers and Transformsjackkoenig
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
Change integration tests to be classes that extend abstract classes. This allows them to be run in parallel. Also expand API to support Verilog resources in integration tests.
2016-07-27Reworked annotation system. Added tenacity and permissibilityAdam Izraelevitz
Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
Transforms are new unit of modularity within the compiler.
2016-04-22Add "normalize" function to FirrtlSpec for easier string comparison testingjackkoenig
2016-04-20Add tests for CHIRRTL mem port definitions.jackkoenig
Including using different clocks and ports defined in when scope.
2016-04-16Add license to testsjackkoenig
2016-04-08Add small test for issue #105jackkoenig
2016-03-15Revamp string literal handlingjackkoenig
2016-03-03Add some integration tests: successful compilation and executionjackkoenig