| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-12-20 | Make submodule inputs void in ExpandWhens (#706) | Jack Koenig |
| 2017-06-13 | Make ExpandWhens delete 'is invalid' for attached Analog components | Jack Koenig |
| 2017-06-13 | Style changes to ExpandWhensSpec | Jack Koenig |
| 2017-05-10 | Update rename2 (#478) | Adam Izraelevitz |
| 2016-12-05 | Bugfix: expand whens not voiding memories (#380) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-10-26 | Improve integration test API and add support for Verilog resources | jackkoenig |
| 2016-09-12 | Added test to check invalid bug was fixed | azidar |
| 2016-05-03 | Add Expand Whens test | jackkoenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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