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path: root/src/test/scala/firrtlTests/DriverSpec.scala
AgeCommit message (Collapse)Author
2017-03-30Make force-append-anno-file work. Fixes #515 (#516)Jack Koenig
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2017-02-01Fix anno in backend (#428)Chick Markley
* fixed up impementation of deleteDirectoryHierarchy Added a few more tests * Round 2 of moving verilog to target dir Only create .f file if some files have been moved Some small style fixes in Driver Restored lost functionality to add -f argument in verilogToCpp Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
2017-01-31Blackboxhelper (#418)Chick Markley
* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory * A little bit of style cleanup * A little bit of style cleanup * Fix the driver, wasn't appending targetDir properly Add some docs * test had wrong value now that targetdir is added to annnos * Now saves a list of all black box verilog files moved into target directory. Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line * Made black box source helper be low to low form Added it to the verilog compiler transforms Added a test to make sure it got there * targetDir annotation is targeted to a CircuitName("All")
2017-01-27Move BackendCompilationUtilities into a util package for use by chisel3. (#400)Jim Lawson
* Move BackendCompilationUtilities into a util package for use by chisel3. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util.
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2016-12-15Delete annotationsTestFile after test (#405)Leonard Truong
2016-12-14Add support for top-level use of MiddleFirrtlCompiler.Jim Lawson
2016-12-08Copy (explicitly) test resource to targetdir. (#392)Jim Lawson
If we execute tests somewhere other than the root of the firrtl project directory (in a parent project directory for examples), the resource file may not be where we expect it. Also clean up imports.
2016-11-23Stringified annotations (#367)Adam Izraelevitz
Restricts annotations to be string-based (and thus less typesafe) Makes annotations more easily serializable and interact with Chisel
2016-11-07make default dir be current directory (#361)Chick Markley
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
* Keep package name + directory structure consistent This annoyed me so heres a PR * fix InferReadWrite references * delete .ConvertFixedToSInt.scala.swo
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
Create a simple system for executions and command line parameters New model for tracking parameters and having those parameters register scopt command to allow the parameters to be set by command line args. Create composable forms of the these parameters to allow separate elements of the chisel3 toolchain to combine these parameters Create execution return structures that simplify return values to earlier toolchain elements