| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-03-26 | Add test for DCE of printf and stop | Andrew Waterman |
| 2018-09-13 | Do not remove ExtMods with no ports by default (#888) | albertchen-sifive |
| 2018-03-23 | Make Register Update Flattening a Transform and Delete Dangling Nodes (#692) | Jack Koenig |
| 2018-02-27 | Refactor Annotations (#721) | Jack Koenig |
| 2017-12-20 | Make submodule inputs void in ExpandWhens (#706) | Jack Koenig |
| 2017-12-12 | Add RemoveWires transform | Jack Koenig |
| 2017-08-01 | DCE for IsInvalid (#629) | Donggyu |
| 2017-06-21 | Add --no-dce command-line option to skip DCE | Jack Koenig |
| 2017-05-17 | Make sure not to DCE input-only extmodules unless specified (#590) | Jack Koenig |
| 2017-05-11 | Improved Global Dead Code Elimination (#549) | Jack Koenig |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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