| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz | |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson | |
| * Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. | |||
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig | |
| * Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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