sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2019-02-05	Do Shr constant propagation in Legalize	Schuyler Eldridge
	This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05	Add RemoveValidIf to -X mverilog	Schuyler Eldridge
	This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization Transform. A test case is included to verify that `is invalid` is properly converted to a connection to zero. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05	Add "mverilog" Compiler Option, Compiler Fixes	Schuyler Eldridge
	This adds "mverilog" to the "--compiler" command line option. This will run the MinimumVerilogCompiler. This additionally fixes the MinimumVerilogCompiler such that DeadCodeElimination will not be run (it's not supposed to be). This is done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog, that strips the DeadCodeElimination step from its parent. Additionally, BlackBoxSourceHelper is removed from the MinimumVerilogCompiler since this will be run by the VerilogEmitter already. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-27	Removed top preamble (#640)	Adam Izraelevitz

2017-03-06	Add ability to emit 1 file per module (#443)	Jack Koenig
	Changes Emitters to also be Transforms and use Annotations for both telling an emitter to do emission as well as getting the emitted result. Helper functions ease the use of the new interface. Also adds a FirrtlExecutionOptions field as well as a command-line option. Use of Writers in Compilers and Emitters is now deprecated.
2016-12-14	Remove scalpels.	Jim Lawson

2016-12-14	Add support for top-level use of MiddleFirrtlCompiler.	Jim Lawson

2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04	Refactor Compilers and Transforms	jackkoenig
	* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-08-25	emit wires instead of registers for invalid randomization	Howard Mao
	Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires.
2016-08-25	update verilog generation test	Howard Mao

2016-07-27	Reworked annotation system. Added tenacity and permissibility	Adam Izraelevitz
	Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz
	Transforms are new unit of modularity within the compiler.