sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-11-04	Refactor Compilers and Transforms	jackkoenig
	* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
2016-08-25	emit wires instead of registers for invalid randomization	Howard Mao
	Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires.
2016-08-25	update verilog generation test	Howard Mao

2016-07-27	Reworked annotation system. Added tenacity and permissibility	Adam Izraelevitz
	Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz
	Transforms are new unit of modularity within the compiler.