sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2020-04-13	Add test-case for explicit padding of SInts in mverilog compiler	Albert Magyar
2020-03-25	Update scalatest 3.1.0 (#1383)	Jim Lawson
2020-02-12	Removed unused imports in src/test/ (#1381)	Jim Lawson
2019-02-05	Do Shr constant propagation in Legalize	Schuyler Eldridge
2019-02-05	Add RemoveValidIf to -X mverilog	Schuyler Eldridge
2019-02-05	Add "mverilog" Compiler Option, Compiler Fixes	Schuyler Eldridge
2017-12-27	Removed top preamble (#640)	Adam Izraelevitz
2017-03-06	Add ability to emit 1 file per module (#443)	Jack Koenig
2016-12-14	Remove scalpels.	Jim Lawson
2016-12-14	Add support for top-level use of MiddleFirrtlCompiler.	Jim Lawson
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-11-04	Refactor Compilers and Transforms	jackkoenig
2016-08-25	emit wires instead of registers for invalid randomization	Howard Mao
2016-08-25	update verilog generation test	Howard Mao
2016-07-27	Reworked annotation system. Added tenacity and permissibility	Adam Izraelevitz
2016-06-10	API Cleanup - AST	Jack
2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz