| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-02-05 | Add "mverilog" Compiler Option, Compiler Fixes | Schuyler Eldridge |
| 2017-12-27 | Removed top preamble (#640) | Adam Izraelevitz |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2016-12-14 | Remove scalpels. | Jim Lawson |
| 2016-12-14 | Add support for top-level use of MiddleFirrtlCompiler. | Jim Lawson |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-08-25 | emit wires instead of registers for invalid randomization | Howard Mao |
| 2016-08-25 | update verilog generation test | Howard Mao |
| 2016-07-27 | Reworked annotation system. Added tenacity and permissibility | Adam Izraelevitz |
| 2016-06-10 | API Cleanup - AST | Jack |
| 2016-05-12 | Restructured Compiler to use Transforms. Added an InlineInstance pass. | Adam Izraelevitz |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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