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* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
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* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.
* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
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* handle uninferred ports gracefully in RemoveCHIRRTL
memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL
* fix CInferTypes
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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Change integration tests to be classes that extend abstract classes. This
allows them to be run in parallel. Also expand API to support Verilog
resources in integration tests.
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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Transforms are new unit of modularity within the compiler.
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Including using different clocks and ports defined in when scope.
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