| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-05-10 | Update rename2 (#478) | Adam Izraelevitz |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-05 | Fix CHIRRTL bugs (#355) | Donggyu |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-10-26 | Improve integration test API and add support for Verilog resources | jackkoenig |
| 2016-07-21 | Added a Chirrtl check for undeclared wires, etc. | azidar |
| 2016-06-10 | API Cleanup - AST | Jack |
| 2016-05-12 | Restructured Compiler to use Transforms. Added an InlineInstance pass. | Adam Izraelevitz |
| 2016-05-12 | Implement File Info | jackkoenig |
| 2016-04-20 | Add tests for CHIRRTL mem port definitions. | jackkoenig |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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