| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-12-18 | Give better error when mport references non-existant memory. (#975) | Paul Rigge |
| 2018-02-27 | Refactor Annotations (#721) | Jack Koenig |
| 2018-02-22 | Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu... | Adam Izraelevitz |
| 2017-06-28 | Promote ConstProp to a transform | Jack Koenig |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz |
| 2017-03-06 | Add ability to emit 1 file per module (#443) | Jack Koenig |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson |
| 2016-11-23 | Stringified annotations (#367) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-04 | Refactor Compilers and Transforms | jackkoenig |
| 2016-09-14 | fix enable signal inferecne for smems' read ports (#289) | Donggyu |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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