sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2019-08-07	Check mems for legal latencies; ban zero write latency. (#1147)	Albert Magyar
	* Check mems for legal latencies; ban zero write latency. * Trigger
2019-08-07	DRY check chirrtl (#1148)	Albert Magyar
	* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks * Add test case for illegal Chirrtl memory in HighForm
2019-02-25	Detect and error on registers with flip in type (#1031)	Albert Magyar

2019-02-22	Add Width Constraints with Annotations (#956)	Albert Chen
	* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2018-09-26	Enforce port uniqueness in Chirrtl/High Checks	Schuyler Eldridge
	Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-08	CheckHighForm should check that Bits MSB >= LSB (#738)	Schuyler Eldridge
	Fixes #700 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-12-20	Verify shl/shr amount is > 0 (#710)	Jim Lawson
	Fixes #527
2017-05-03	Add checks on register clock and reset types (#33) (#553)	Albert Magyar
	Remove infix notation on calls with side effects.
2016-12-08	Clk2clock - rename the implicit "clk" module input "clock" (#387)	Jim Lawson
	* Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
	Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-08-16	add test case for clock type connection (#239)	mwachs5

2016-07-25	Detects and flags cyclic module loops	chick

2016-06-10	API Cleanup - AST	Jack
	trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-05-24	Added Errors class and fixed tests.	azidar
	Canonicalizes catching/throwing PassExceptions.
2016-05-12	Implement File Info	jackkoenig

2016-04-26	Add test for recursive check for whether BundleType contains flips	Adam Izraelevitz