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* Pull out common test utilities into a separate package
* Project a fat jar for test utilities
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* Add constant prop to async regs
* Added another test of no reset value but constant assignment
* Clarify name of updateNodeMap
* Update constant assignment of async reset to not be inferred as a latch, works with donttouch
* Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch"
This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
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[skip formal checks]
Adds new InlineCastsTransform to the VerilogEmitter which removes
Statements that do nothing but cast by inlining the cast Expression
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Recursive literal lookup needs to be guarded against combinational loops
Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
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Major features:
- Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz.
- Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp
- Refactored width/bound inferencer into a separate constraint solver
- Added transforms to infer, trim, and remove interval bounds
- Tests for said features
Plan to be released with 1.3
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* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1>
* Enhance async reset initial value literal check to support aggregates
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Fixes #219
* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers
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