| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-02-06 | Add constant prop to async regs (#1355) | Adam Izraelevitz |
| 2020-02-06 | Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359) | Albert Magyar |
| 2020-01-07 | Remove unnecessary $signed casts for PrimOps in Verilog Emitter | Jack Koenig |
| 2019-11-05 | Move CheckResets after CheckCombLoops (#1224) | Jack Koenig |
| 2019-10-18 | Upstream intervals (#870) | Adam Izraelevitz |
| 2019-08-13 | Infer reset (#1068) | Jack Koenig |
| 2019-02-14 | Asynchronous Reset (#1011) | Jack Koenig |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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