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* add os-lib to dependency.
* use os-lib in Z3ModelChecker
* fix for review by Kevin.
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This finally removes all randomization code from the transition
system conversion and into a separate pass using DefRandom nodes.
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* SMT: memory port inout fields cannot be used as RHS expressions
* smt: add end2end check for read enable modelling
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With this PR the smt backend now supports memories
with more than two write ports and the conservative
memory modelling can be selectively turned off with
a new annotation.
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Fix scalafmtCheckAll failures that snuck through
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: add test for write port collision
* smt: add missing call to insertDummyAssignsForMemoryOutputs
* smt: fix typo in write port code
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: add tests for assert name clashes
* smt: ensure unique signal names with a namespace
this fixes issues #1934
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If there is more than one clock, this will be detected and
the user will be promted to run the StutteringClock transform.
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This adds an experimental new SMTLib and Btor2 emitter
that converts a firrtl module into a format
suitable for open source model checkers.
The format generally follows the behavior of yosys'
write_smt2 and write_btor commands.
To generate btor2 for the module in m.fir run
> ./utils/bin/firrtl -i m.fir -E experimental-btor2
for SMT:
> ./utils/bin/firrtl -i m.fir -E experimental-smt2
If you have a design with multiple clocks
or an asynchronous reset, try out the new StutteringClockTransform.
You can designate any input of type Clock to be your
global simulation clock using the new GlobalClockAnnotation.
If your toplevel module instantiates submodules,
you need to inline them if you want the submodule
logic to be included in the formal model.
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