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Scala FIRRTL Compiler for chiselX
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2021-05-17
Use os-lib to rewrite Z3ModelChecker (#2223)
Jiuyang Liu
2021-03-09
SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)
Kevin Laeufer
2021-03-08
SMT: memory port inout fields cannot be used as RHS expressions (#2105)
Kevin Laeufer
2021-03-04
SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)
Kevin Laeufer
2021-03-02
Remove Scala 2.11 (#2062)
Jack Koenig
2021-01-19
Restore scalafmt CI check (#2047)
Jack Koenig
2021-01-19
smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)
Kevin Laeufer
2020-12-02
smt: add support for uninterpreted ext modules (#1994)
Kevin Laeufer
2020-11-11
smt: add support for write-first memories (#1948)
Kevin Laeufer
2020-11-10
Fix SMT Memory Bug (#1942)
Kevin Laeufer
2020-11-09
smt: ensure that all signals have a unique name (#1943)
Kevin Laeufer
2020-09-16
Change to Apache 2.0 License (#1901)
Chick Markley
2020-08-26
smt: ignore clock signals when converting to transition system (#1866)
Kevin Laeufer
2020-08-14
All of src/ formatted with scalafmt
chick
2020-08-15
experimental SMTLib and btor2 emitter (#1826)
Kevin Laeufer
