sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-10-26	Add RawString ExtModule parameter support	jackkoenig
	While unsafe, this supports Verilog parameter types. Tests now require Verilator 3.884+ to pass.
2016-10-26	Add Support for Parameterized ExtModules and Name Override	jackkoenig
	Adds support for Integer, Double/Real, and String parameters in external modules. Also add name field to extmodules so that emitted name can be different from Firrtl name. This is important because parameterized extmodules will frequently have differing IO even though they need to be emitted as instantiating the same Verilog module.
2016-10-26	Add ExtModule Tests	jackkoenig

2016-10-07	Add test for Firrtl mems with no ports (#327)	Jack Koenig

2016-09-12	Add LegalizeSpec for testing Verilog Legalization pass	Jack

2016-05-12	Restructured Compiler to use Transforms. Added an InlineInstance pass.	Adam Izraelevitz
	Transforms are new unit of modularity within the compiler.
2016-05-03	Add Expand Whens test	jackkoenig

2016-05-03	Make simulations that time out fail when run in firrtlTests	jackkoenig

2016-04-20	Add tests for CHIRRTL mem port definitions.	jackkoenig
	Including using different clocks and ports defined in when scope.
2016-04-20	Fix top.cpp reset race condition #137	jackkoenig

2016-04-08	Add small test for issue #105	jackkoenig

2016-03-15	Revamp string literal handling	jackkoenig

2016-03-03	Add some integration tests: successful compilation and execution	jackkoenig

2016-02-23	Add rocket regression, just runs rocket.fir through Verilog compiler and ↵	Jack
	compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip